1. Field of the Invention
The present invention relates to methods for forming transistors, and more particularly to methods for forming thin film transistors.
2. Description of the Related Art
Thin film transistors (TFT) are the basic building blocks of large area electronic circuits such as those used in the backplanes of active matrix liquid crystal displays (AMLCD) of the type often used in flat panel monitors and televisions. In these applications, TFT circuits are used to control the activation of pixels that make up the display. In some applications, thin film circuits may be produced over non-planar surfaces and in other applications they may be required to be optically transparent to visible light. Yet in other applications, they may be fabricated on flexible substrates. Conventional transistors made on single crystal substrates cannot generally be used in these unique applications.
Historically, TFTs have been made from amorphous silicon (a-Si) or poly-silicon (p-Si) films to satisfy the application requirements described above, rather than the single crystal Si as it is the case with conventional electronic circuits such as microprocessor circuits of modern computers. Transistors made from a-Si and p-Si, however, suffer from a number of deficiencies including low electron mobility, light sensitive operation, limited switching ratios, and/or poor threshold voltage uniformity. These deficiencies make a-Si TFTs generally unsuitable for the current generation of display circuit applications that demand higher switching speeds and accuracy.
In recent years, metal-oxide semiconductors have been considered for display electronics applications. Among several metal-oxide semiconductors that are useful for thin film applications, Zn, In, Sn, Ga, and Hf containing metal-oxides have shown good promise. One of the more promising metal-oxide semiconductors for thin film and transparent transistor applications is ZnO. ZnO is transparent because of its wide band gap (3.4 eV), has high thin film electron mobility, and can be easily prepared by several deposition techniques. ZnO and related composition thin film transistors have been shown to be suitable for high performance circuit applications beyond display electronics because of their superior electronic properties. Some of these applications include microwave signal amplification, microwave signal switching and mixing, high speed logic circuits, and high speed control electronics. While ZnO is a simple binary compound and its composition is readily controlled in manufacturing environment, other metal-oxide based thin film semiconductors are also useful when they are a mixed combination of several metal-oxides. For example, indium zinc oxide (IZO) or indium zinc gallium oxide (IGZO) are ternary and quarternary compound semiconductors that are also being used.
The speed of thin film transistors relates directly to their gate length, which must be kept as short as possible to lower electron transport time between electrodes and improve its high frequency response characteristics. Since current density is proportional to W/L, where W is the gate width and L is the gate length, reduced gate length improves device current capability. Photolithography, which is the main technology used in defining electrode dimensions for TFTs, is limited in scope to fabrication line widths larger than 1 micrometer. Advanced lithography techniques applied to modern single crystal microelectronics rely on extremely well controlled substrate surface flatness and resist uniformity. These conditions cannot be maintained for thin film electronics and therefore only large gate lengths have been possible in the past. This is especially true for metal oxide TFTs, whose fabrication technology is less mature than Si.
In a bottom gate TFT 10, as shown schematically in FIG. 1, a first layer to be fabricated on a substrate 12 is a conductive gate metal 14. Other layers are fabricated over this layer in sequence during fabrication. Unwanted portions of each layer are removed by etching while protecting the portions of the layer with protective films such as photoresist. A major difficulty in metal oxide TFT manufacturing is the fabrication of source 16 and drain 18 contact metals over a semiconductor channel layer 20. The fabrication processes used to establish source 16 and drain 18 contacts often cause damage to the channel layer 20.
There are multiple sources of damage in conventional processes. One source of damage is the chemicals used in lithography techniques. In a commonly used lift-off technique, where the areas are defined in a photoresist layer before the deposition of source and drain metals, the semiconductor surface is exposed to both the photoresist and its developer. Both the photoresist and the developer can damage the semiconductor surface by etching it or by contaminating it. In an alternative approach, continuous metal layers may be fabricated over the entire surface and unwanted regions of this metal layer can be removed by masking and etching. There are at least two sources of damage in this method. First, the surface may be contaminated by the residue of the metal or the etchant due to incomplete metal removal. The etchant may also leave residual contaminants. Second, most chemicals used for etching the metal layer also causes etching of the semiconductor surface. Metal oxides, such as ZnO, are highly soluble in most common acids and bases, even when they are highly diluted. Even oxidizing chemicals such as hydrogen peroxide alone can damage ZnO surface. Many of the common reactive ion etching techniques based on chlorine chemistry, such as BCl3 and CCl4, also etch or damage the ZnO film.
Because of these well-known fabrication issues, a common approach is to make use of physical masks, typically made of thin metal layers, to shield, during layer deposition, the portions of the surface where separation between source 16 and drain 18 contacts is desired. The physical mask layer fabrication method has severe limitations in the feature sizes that can be used. Instead of the desired dimensions in micrometers, this method is only capable of producing devices with feature sizes of millimeters. The placement accuracy of the physical mask over the wafer is not well controlled resulting in gross errors in registering contact layers with respect to gate metal. The edges of metal lines fabricated in this method have poor definition due to shadowing effects and result in uncontrolled device parameters.
A method of overcoming part of this problem was described in U.S. Pat. Nos. 7,910,920 and 8,119,465 and U.S. Publication No. 2006/0043447. According to the various versions of the method described, a protective insulating layer is produced over the channel layer first. Portions of this layer are removed in a dry etch process without removing the underlying ZnO channel layer. Source and drain contact layers are produced over the protective layer and allowed to make contact with the channel layer in the regions where the protective layer was previously removed by dry etching. This method adds several fabrication steps in manufacturing and results in degradation of device performance due to damaged layers or contamination resulting from additional processing steps. For example, the fabrication of silicon dioxide or silicon nitride as the protective layer introduces hydrogen and/or nitrogen into the channel layer. Both of these contaminants are dopants for ZnO and therefore increase the channel conductivity. The presence of the protective layer on the channel modifies the device characteristics depending on the charges in this protective layer and at the interface between it and the channel layer.
A variation of the protective layer approach was described in U.S. Pat. No. 8,129,717. In this approach, the protective layer is a highly doped semiconductor, which also serves as an intermediate contact layer under the source and drain electrodes. This protective layer absorbs damage during etching of the metal between source 16 and drain 18 electrodes. It is subsequently removed by etching. The fabrication and the removal of this protective layer complicate the process and introduce sources of fabrication uncertainties across the wafer.
In another method described in U.S. Pat. No. 7,915,075, source and drain contact metal is etched in a chlorine based plasma such as CCl4, BCl3, or SiCl4. Since these etch types are not highly selective to ZnO or other metal oxide semiconductors, a portion of the active channel region is also etched. Apart from the fact that such etching conditions produce contaminated surface, they also result in uneven etch rates across the wafer. The resulting device characteristics are therefore not uniform across the wafer.
In a similar technique described in U.S. Pat. No. 7,994,510, the source and drain metal is first fabricated on plasma treated semiconductor film and then etched to reveal the semiconductor surface. Further etching of the semiconductor surface is needed, however, to remove the damaged layer.
In the approach taken in U.S. Pat. No. 8,187,919, the damaging effects of etching metal on the active layer is mitigated by the fabrication of the semiconductor layer after the source and drain contacts are fabricated. However, it is well known that ZnO fabricated on top of metal layers often produces non-ohmic or high resistivity electrical properties, unlike the low resistivity ohmic properties of ZnO layers that are contacted from the top surface.
As set out above, a critical dimension that influences device performance is the distance between the source and the drain electrodes. This distance is the effective device gate length 22, as shown in FIG. 1. The gap between source 16 and drain 18 electrodes can be produced by several techniques including “lift-off” and “etching.” In the lift-off technique, photoresist patterns are fabricated by opening areas in the resist corresponding to the electrodes. These areas are filled with evaporated metal. Excess metal over the photoresist is removed by dissolving it in solvent. In the etching technique, the metal layer is first produced over the entire surface by for example sputtering techniques. Photoresist patterns are then produced over the metal layer to mask areas that correspond to the electrodes. The unprotected metal surfaces are etched until all metal in these areas are removed. As indicated above, it is important that the etchant used to remove the metal layer does not also etch the semiconductor layer or damage its surface. In either approach, the critical dimension is the gate length 22. Using photolithography, the minimum gate length that can generally be produced is about twice the wave length of the light used to expose the photoresist. The highest speed metal oxide TFTs using this technique had about 1 micrometer gate lengths. Similar size gate lengths were achieved for amorphous Si based TFTs as described in U.S. Pat. No. 7,537,979.
An alternative photolithography-based fabrication method was described in U.S. Pat. Nos. 5,532,180 and 5,872,370. In this approach, the source and drain electrodes are fabricated separately. By relying on positioning accuracy of the equipment, these transistor electrodes were placed closer to each other than the optical resolution of the photolithography tool. However, these approaches introduce an additional process step which can be a source of additional surface damage to the semiconductor layer. Also, the positioning approach may additional introduce alignment errors in both X and Y dimensions so that across the wafer there may be rotational misalignments. The minimum gate length sizes were limited to 1-4 micrometers due to these restrictions.
Shorter gate lengths can be fabricated using expensive lithography techniques such as “Leading-edge KrF Scanner” technique with special photoresists, near-field lithography, nanoimprint technology, and electron beam lithography. These sophisticated lithography techniques are slow, expensive and generally not compatible with the thin film electronics produced over large area substrates.
Accordingly, there is a need in the art for methods of fabricating thin film transistors without the drawbacks or difficulties associated with contemporary fabrication methods.